1. Field of the Invention
The present invention relates generally to a method and arrangement of multiplexing a plurality of serial data using "wired-OR" connection. The plurality of serial data, before being multiplexed, are generated from the corresponding parallel data via parallel/serial conversion.
2. Description of the Prior Art
It is known in the art to multiplex or combine a plurality of serial data in the same transmission medium using a so called "wired-OR" connection.
Before turning to the instant invention it is deemed preferable to discuss, with reference to FIGS. 1-6, a known arrangement of multiplexing a plurality of serial data using "wired-OR" coupling.
Reference is made to FIG. 1, wherein there is shown an overall arrangement of a multiplexor 10 in block diagram form. The multiplexor 10 includes four circuit units 12a-12d arranged in parallel. Each of the units 12a-12d, which may be configured using LSI (Large Scale Integration) techniques, is provided with a parallel data input PI, two address inputs ADa and ADb, a serial data output SO, and a reset terminal R.
The units 12a-12d are arranged to convert respectively the parallel data PDT1-PDT4 applied thereto at the inputs PIs into the corresponding serial data which are respectively outputted as SD1-SD4 in a predetermined transmission order.
Each pair of the address inputs ADa and ADb of the units 12a-12d, received address bits (2 bits in this instance) which are used to discriminate or specify one of the units 12a-12d in order to define the predetermined transmission order. The address input ADa receives LSB (least significant bit) while the address input ADb is supplied with MSB (most significant bit).
The circuit units 12a-12d are reset, by a system reset signal SRST, at the beginning of the operation of the system including the multiplexor 10 and, subsequently, receive respectively four parallel data PDT1-PDT4. The units 12a-12d are arranged to convert the parallel data PDT1-PDT 4 into corresponding serial data SD1-SD4 and then transmits them in the predetermined order as an output Sout over a transmission line 14. Each of the parallel data PDT1-PDT4 includes 16 bits in this case.
A pulldown resistor 16 is provided between ground and each of the serial data outputs SO. Accordingly, each of the units 12a-12d acquires ground level potential in the case where there is no output from each of the units 12a-12d.
FIG. 2 is a block diagram which shows the arrangement of the circuit unit 12a in detail. It should be noted that each of the units 12b-12d is configured in exactly the same manner as the unit 12a. The FIG. 2 arrangement includes, a transmission pause detector 18, a transmission order determiner 20, a control signal generator 22, a shift register 24, a cyclic redundance code (CRC) bits adder 26, a manchester encoder 28, a wave shaper 30, and a driver 32, all of which are coupled as illustrated.
FIG. 3 is a block diagram showing the transmission order determiner 20 of FIG. 2 in detail. As shown, the determiner 20 includes a 2-bit pre-loadable up-counter 32, two inverters 34 and 36, and an AND gate 38. Each of the counterparts of the units 12b-12d is configured in exactly the same manner as shown in FIG. 3.
FIG. 4 is a chart showing a code format of each of the serial data SD1-SD4 to be multiplexed. As shown, the code format of FIG. 4 includes 25 bits in total and begins with start bits (3-bit) which are followed by address ID bits (2-bit), data bits (16-bit), CRC bits (2-bit) and a stop bit. The 3rd to 25th bits of the code format are manchester encoded.
The operations of the FIG. 1 arrangement will be discussed with reference to FIGS. 2-4 and a timing chart shown in FIG. 5.
When the system reset signal SRST goes high at time point TO, each of the units 12a-12d acquires the corresponding address bits at the corresponding 2-bit un-counter (viz., preloading the initial counter content). The two inverters (34, 36 in the case of the unit 12a) are provided prior to the data inputs DATAa and DATAb of the counter (32 in the case of unit 12a). Accordingly, the up-counters of the units 12a-12d are initially set as shown below:
Up-counter 32 of the unit 12a : 11 PA0 Up-counter (not shown) of the unit 12b: 10 PA0 Up-counter (not shown) of the unit 12c: 01 PA0 Up-counter (not shown) of the unit 12d: 00
Thus, an address ID (Identification) signal ADID, which is the output of the AND gate 38 of the unit 12a, assumes a high level (viz., logic 1) at time point TO when the system reset signal SRST goes hig. (It should be noted that time delays of signal propagation via elements are ignored for the purposes of simplifying the time charts of the instant disclosure.) It is understood that each of the AND gates of the units 12b-12d, which correspond to and the AND gate 38 of FIG. 3, continues to issue a low level (viz., logic 0) at time point TO.
In FIG. 2, the ADID is applied to the control signal generator 22 which in turn issues the start bits and then the stop bit over a line 40. The shift register 24 receives the start bits, the address ID bits (00), data bits, and the stop bit in this order. The output of the shift register 24 is applied to the CRC bits adder 26 which inserts the CRC bits between the data bits and the stop bit in response to a control signal applied from the control signal generator 22 over a line 42. The CRS bits are known in the art and further are not directly concerned with the present invention, and hence the description thereof will be omitted.
The encoder 28 is arranged to manchester encode part of the output of the CRC bits adder 26 (viz., the 3rd to 25th bits) in response to a control signal applied from the control signal generator 22 over a line 44. Subsequently, the output of the manchester encoder 28 undergoes wave shaping at the wave shaper 30 and then is applied to the serial data output SO via the driver 32. At this time, the driver 32 has been rendered active by a control signal from the control signal generator 22 via a line 46.
The serial data SD1 appears at the output SO of the unit 12a between time points T1-T2 as shown in FIG. 5. In the event that the serial data SD1 terminates at time point T2, the potential at the output terminal SO falls down to ground via the pulldown resistor 16. When the transmission pause detector 18 detects that the ground potential at the output terminal SO continues for a predetermine time duration, the detector 18 applies, at time point T3, a transmission pause detection pulse Z (Z1) to the counter 32 of the transmission order determiner 20. The pause detection pulse Z (Z1) is used to count up the contents (00 in this instance) by one binary number (viz., counts up to 01). Accordingly, the signal ADID of the unit 12a assumes a low level (viz., logic 0).
Similarly, each of the transmission pause detectors (not shown) of the units 12b-12d detects the transmission pause (interruption) and generates the pause detection pulses Z1 at time point T3. In this instance, only the unit 12b generates the serial data between time points T4-T5.
Subsequently, the units 12c, 12d generate the serial data SD3, SD4 in response to transmission pause pulses Z2 and Z3, respectively. After one cycle of the serial data generations of the units 12a-12d is completed, the units 12a-12d generate the serial data SD1-SD4 during the next cycle in response to transmission pause detection pulses Z4, Z5, Z6, . . . at time points T12, T15, T18, . . . respectively.
As mentioned above, once the system reset signal SRST goes high, the units 12a-12d successively generate the serial data thereof according to the predetermined order in response to the occurrences of the transmission pause pulses Z1, Z2, Z3, . . . In other words, when the system including the multiplexor 10 initiates the operations thereof, the system reset signal SRST continues to hold a logic 1 until the system is de-energized. Therefore, the above mentioned prior art has encountered the problem which will be discussed with reference to a timing chart shown in FIG. 6.
It is difficult that threshold levels of the units 12a-12d for detecting the system reset signal SRST are not fixed to the same level. Therefore, if the unit 12a detects that the system reset signal SRST falls down and then goes high at time points T8' and T9 due to external noises, then the predetermined transmission order of the unit 12a is disturbed. This means that the serial data collision is invited during time points T10-T11 and continues in the following cycles. The prior art is unable to correct these problems until the overall system is awkwardly initialized. This means that a long time passes until restoring the overall system to the correct operations.